1. Field of the Invention
The present invention relates to chip stacks in which a plurality of integrated circuit chips arranged in a stack are electrically connected with a supporting substrate board in a desired pattern.
2. History of the Prior Art
It is known to provide a chip stack in which a plurality of integrated circuit (IC) chips such as memory chips are mounted on a substrate board and are electrically interconnected in desired fashion. Typically, the chips have electrical contacts which are coupled in common or in parallel to contacts on the substrate board, as well as unique contacts which are coupled individually to the substrate board to the exclusion of the other chips.
A number of different arrangements have been provided for electrically interconnecting IC chips in a stack. For example, electrical conductors which may comprise thin-film metal on an insulating base may be disposed generally perpendicular to the planes of the generally planar chips so as to connect those conductors on each chip which are exposed through openings in an insulating layer. Where the chip packages are assembled into a stack, electrical connections may be accomplished by lead frames or solder strips extending along the sides of the stack and attached to the electrical contacts of the chips.
One common technique for providing the desired electrical interconnections in a chip stack is to form a stack of chips having bonding pads disposed on the chips adjacent the outer edges thereof. After assembling the stack of chips, the chip edges are ground flat and polished before sputtering an insulating layer thereon. The bonding pads on the edges of the chips are masked during the sputtering process to avoid covering them with the insulating layer. Next, a metal layer is sputtered onto the entire edge of the stack in conjunction with photomasking which forms conductor traces of the metal layer in desired locations for connecting the bonding pads. Procedures such as this are complicated and expensive to carry out.
An example of a vertical stack of IC chips is provided by U.S. Pat. No. 4,956,694 of Floyd Eide, which patent issued Sep. 11, 1990, is entitled "Integrated Circuit Chip Stacking", and is commonly assigned with the present application. The Eide '694 patent describes a stack of chip carriers on a printed circuit board. Each chip carrier packages an IC chip having various terminals. The input/output data terminals, power terminals and ground terminals of the various chips are coupled in parallel, while each chip is capable of being individually accessed to enable the chip.
Another technique for electrically interconnecting the chips in the stack is shown and described in U.S. Pat. No. 5,313,096 of Floyd K. Eide, which patent issued May 17, 1994, is entitled "IC Chip Package Having Chip Attached To And Wire Bonded Within An Overlying Substrate", and is commonly assigned with the present application. The Eide '096 patent describes a chip stack formed from a plurality of chip packages, each of which comprises an IC chip or die of thin, planar configuration mounted on the underside of a relatively thin, planar multi-layer substrate. Contacts at the outer edges of the substrate are electrically connected to the chip through conductors disposed within the substrate and extending to electrical contacts within an aperture in the substrate. The electrical contacts within the aperture are wirebonded to contacts on the upper active surface of the chip in desired fashion. Following that, the aperture in the substrate is filled with epoxy or other filling material which is ground or backlapped to provide an upper surface thereof which is flat and continuous with an upper surface of the substrate opposite the chip. The chip packages may be completed prior to testing to determine optimum placement within a stack to be formed, with a bonding option array of conductors within another aperture in the substrate thereof being used to program the chip package in a desired manner. Upon assembly of the chip packages into a stack, the electrical interconnection thereof is accomplished using conductive films which are formed on the side surfaces of the chip packages in electrical contact with the contacts of the outer edges of the substrates of the chip packages. Solder strips which are then formed in contact with the conductive films and the opposite electrical contacts of each package form an array of parallel conductors.
A common technique for packaging chips for purposes of forming a stack thereof is to encapsulate the chip in a plastic body with the electrical contacts of the chip being wire bonded to leads extending from opposite ends of the body. These so-called thin small outline packages (TSOPs) may then be stacked together and covered with a potting compound to hold the stack together. Grinding the ends thereof exposes the leads of the TSOPs so that metal can be sputtered onto the ground surfaces. After photomasking, the sputtered metal is etched away from desired areas, and the photomasking is then removed. Following that, the stack may be attached to a substrate. This technique for forming a stack of TSOPs involves an 8-step process which is difficult, time consuming and expensive. In addition, the differences in the materials of the chip stack and the substrate require that the stack be coupled to the substrate using flexible electrical leads to provide stress relief as the stack and the substrate expand and contract at different rates in response to changes in ambient temperature.
Thus, while chip stacks of the type described provide various advantages over the earlier chip stack arrangements of the prior art, there is still a need for chip stacks having certain design characteristics. For one thing, it would be desirable to provide a chip stack which is easy to assemble using a simple process involving only a few steps. Also, a chip stack of relatively simple and economical configuration would be desirable. The stack should be easily disassembled in the event that a defective chip must be replaced. The design of the stack should minimize stresses which occur as a result of expansion and contraction of the various materials within the stack and the attached substrate as the ambient temperature changes. A further and desirable feature would be the ability to electrically interconnect the chips in a stack for ease of addressing individual chips, such as to enable them, as well as for common interconnection of other chip terminals.